1. Field of the Disclosed System
The present disclosed system relates to field-programmable gate arrays, and more particularly, to an apparatus and method for creating power-on-reset and clock signals for memory operation immediately after applying a power supply.
2. Description of the Related Art
A field-programmable gate array (FPGA) is an integrated circuit (IC) that includes a two-dimensional array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. The cells are linked to one another by programmable buses. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing all Boolean functions of a few variables. The cell types are not restricted to gates. For example, configurable functional groups (“FGs”) typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain at least one flip-flop. Some types of logic cells found in FPGAs are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for small-scale manufacture.
FPGAs typically include a physical template that includes an array of circuits, sets of uncommitted routing interconnects, and sets of user programmable switches associated with both the circuits and the routing interconnects. When these switches are properly programmed (set to on or off states), the template or the underlying circuit and interconnect of the FPGA is customized or configured to perform specific customized functions. By reprogramming the on-off states of these switches, an FPGA can perform many different functions. Once a specific configuration of an FPGA has been decided upon, it can be configured to perform that one specific function.
The user programmable switches in an FPGA can be implemented in various technologies, such as ONO antifuse, M-M antifuse, SRAM memory cell, Flash EPROM memory cell, and EEPROM memory cell. FPGAs that employ fuses or antifuses as switches can be programmed only once. A memory cell controlled switch implementation of an FPGA can be reprogrammed repeatedly. In this scenario, an NMOS transistor is typically used as the switch to either connect or disconnect two selected points (A, B) in the circuit. The NMOS′ source and drain nodes are connected to points A, B respectively, and its gate node is directly or indirectly connected to the memory cell. By setting the state of the memory cell to either logical “1” or “0”, the switch can be turned on or off and thus point A and B are either connected or disconnected. Thus, the ability to program these switches provides for a very flexible device.
FPGAs can store the program that determines the circuit to be implemented in a RAM or PROM on the FPGA chip. The pattern of the data in this configuration memory (“CM”) determines the cells' functions and their interconnection wiring. Each bit of CM controls a transistor switch in the target circuit that can select some cell function or make (or break) some connection. By replacing the contents of CM, designers can make design changes or correct design errors. The CM can be downloaded from an external source or stored on-chip. This type of FPGA can be reprogrammed repeatedly, which significantly reduces development and manufacturing costs.
In general, an FPGA is one type of programmable logic device (PLD), i.e., a device that contains many gates or other general-purpose cells whose interconnections can be configured or “programmed” to implement any desired combinational or sequential function. As its name implies, an FPGA is “field-programmable”, meaning that the device is generally programmed by designers or end users “in the field” via small, low-cost programming units. This is in contrast to mask programmable devices which require special steps in the IC chip-manufacturing process.
A field-programming unit typically uses design software to program the FPGA. The design software compiles a specific user design, i.e., a specific configuration of the programmable switches desired by the end-user, into FPGA configuration data. The design software assembles the configuration data into a bit stream, i.e., a stream of ones and zeros, that is fed into the FPGA and used to program the configuration memories for the programmable switches or program the shift registers for anti-fuse type switches. The bit stream creates the pattern of the data in the configuration memory CM that determines whether each memory cell stores a “1” or a “0”. The stored bit in each CM controls whether its associated transistor switch is turned on or off.
In RAM based FPGA devices, the memory array may be required to be cleared on power up so that the FPGA remains in an inactive state before loading the configuration bit stream mentioned above. The clearing operation usually occurs immediately after the power supply is applied to the FPGA. If the FPGA is on a circuit board and receives power from the circuit board, then the power supply to the FPGA may gradually rise to the operating voltage due to the large capacitance normally associated with circuit boards.
A RAM-based FPGA often draws a large power-up current. The initial power-up current required by the FPGA may be partially or completely due to unsuccessful attempts of the FPGA to clear its internal configuration memory. As the supplied voltage gradually rises to the operating voltage, the device begins attempting to clear the memory cells, but if the voltage is too low, the clearing operations will be unsuccessful. These unsuccessful clearing operations can draw significant current that is wasted on the device and by clamping down the voltage can increase the time it takes for the power supply voltage to reach operating levels. Clearing the configuration memory would be a burden on the external power supply if it has the requirement of having to supply a large initial current. In addition, the large initial current required to clear the configuration memory may also clamp down the power supply voltage to the FPGA due to resistance on the external power line and the bond wires from the FPGA package pins of power supply to the device.
FIG. 1 a is a simplified schematic diagram illustrating a typical memory array 10 of a field programmable gate array. Memory array 10 comprises a plurality of memory cells 30. Memory cell 30 will be discussed in greater detail below. Memory cells 30 are coupled to bit-bar lines 14 and row lines 18. Row lines 18 are coupled to a row address line 16 through a row decoder 15 comprising an AND gate 22, which represents the “Row Decoding Function Block”, and a driver 24. Row address line 16 is coupled to row counter 17.
Bit-bar lines 14 are coupled to a column address line 20 through a column decoder 25 and bit driver 12. Column address line 20 is coupled to column counter 19. Column decoder 25 comprises a NAND gate 26, which represents the “Column Decoding Function Block”. Bit-line driver 12 comprises a two-input NAND gate 28 having a first input coupled to column address line 20 through column decoder 25. Thus, when the memory clear bar 32 is at logic “0”, all bit-bar lines 14 will be driven to logic “1.” Two-input NAND gate 28 has a second input coupled to memory clear line 34, which is coupled to memory clear bar 32 during a memory clear operation. Memory array 10 typically contains all the configuration data in an FPGA device.
To address this problem, power-on-reset circuit blocks are used inside the FPGA to reset the programming and control logic circuitry on power-up of the device. For example, in an FPGA device, resetting the programming and control circuitry switches all programming elements to the same logic level (e.g., to “0” or “low”). Then when the configuration bit stream is loaded into the device, only the elements to be programmed are accessed and switched. Power-on-reset circuit blocks are well known to those of ordinary skill in the art. Power-on-reset circuitry may also be used to inhibit memory clearing or programming when the main supply voltage (“VDD”) is too low. Generally, the power-on-reset circuitry is an analog circuit and is sensitive to the transistor parameters and it is, therefore, very hard to track the actual minimum voltage required to clear or write to a memory cell (“VDD_MIN”) with the power input voltage level that releases the power-on-reset signal when the process parameters or temperature change.
FIG. 1b is a simplified schematic diagram illustrating a typical memory cell 30 as commonly used in the memory array of FIG. 1a. Memory cell 30 usually requires a voltage above a minimum voltage level VDD_MIN in order to be successfully cleared or written. Memory cell 30 comprises a pair of cross-coupled pass transistors and is a type commonly used in FPGA devices and well known to those of ordinary skill in the art. The data is driven from a bit-line driver (not shown) onto the bit-line through a pass gate 38 having a gate coupled to row line 18 and through memory cell 30. Because of the variation of the fabrication process parameters, the parameters of the transistors of the memory cell will change. Thus, the VDD_MIN required to successfully clear or write memory cell 30 may be different from one FPGA device to another. Temperature may also affect the parameters of the transistors, and thus is an additional parameter that may effect VDD_MIN.
FIG. 2A is a simplified bock diagram of a conventional power-on-reset circuit block. A power-on-reset functional block 100 comprises a power-on-reset circuit which generates a reset signal (PORST) through reset signal line 104. Power-on-reset circuits are well known to those of ordinary skill in the art.
The timing diagram of FIG. 2B shows the voltage input to an integrated circuit device. As shown in the timing graph in FIG. 2B, when a power supply to, for example, a circuit board, is first switched on, the power supplied to the integrated circuit device takes some time to reach the operational voltage level.
A conventional power-on-reset circuit block sends a reset signal once the supply voltage has reached a pre-determined level. For example, analog circuitry within the power-on-reset circuit block may be used to determine when the supply voltage has reached a certain level. This level is set at a constant figure by the characteristics of the analog circuit. For various reasons, the predetermined level may or may not correspond to the actual level required to reset the device. For example, the temperature of the device could affect the actual voltage required.
Other conventional power-on-reset circuit blocks, rather than directly determining the voltage being input, employ a built-in time delay so that the reset signal (PORST) is not activated until a minimum amount of time has elapsed following the initial application of the power supply. A simple time delay does not test the level of the power supply voltage, but only delays passing the voltage to the device for a predetermined amount of time, which may over or under-estimate the actual time required to reach the minimum voltage level.
Hence, there is a need for an apparatus and a method of generating a power-on-reset signal or other device function activation signal that more accurately determines the minimum voltage input required to reset the device (or perform another device function) and only releases the signal when the input voltage is above an actual minimum required voltage, rather than a predetermined estimate. In addition, there is a need for a power-on-reset circuit that can provide an on-chip clock signal that will only clock when the input voltage is high enough for memory clearing and writing or some other device function (i.e. remains static until the power-on-reset signal changes state from 0 to 1).